<title>CMOS Master-Slave Flip-Flop</title>
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This is a <a href="e-masterslaveff.html">master-slave flip flop</a> implemented with
<a href="http://en.wikipedia.org/wiki/CMOS">CMOS</a> inverters and transmission gates.
When the clock is low, the flip-flop retains its state.  The first stage flip-flop,
the master, consists of two inverters at the
upper left which are connected in a positive feedback
configuration so that their outputs do not
change.  When the clock goes high, the D input is transmitted to the first stage,
and the second stage (the slave) is connected in positive feedback to ensure
that the output still does not change.  When the
clock goes low again, the second stage is set to the same state as the first stage,
changing the output.  So the output changes only when the clock has a negative
transition.

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<br>Generated Tue Dec  7 2010
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